 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| NJU6515 -1- ver.2006-08-22 10-character 1-line lcd driver with smooth scroll function general description the NJU6515 lcd driver can realize 10-character 1-line and max. 118 icons display. it contains voltage boost, regulator, bleeder resistor, general output ports, oscillator, microprocessor interface circuit, instruction decoder, character generator rom/ram and common and segment drivers. the NJU6515 can realize display with 1-wire serial data from mpu, and its low operation voltage and low current consumption make it very suitable for the space-conscious products. features 10-character 1-line maximum 118 icon display 1-wire serial interface display data ram 11 x 8 bits character generator rom 6,720 bits (192 characters for 5 x 7 dots) character generator ram 77 x 5 bits (11 patterns for 5 x 7 dots) icon display ram 118 bits duty ratio 1/8, 1/9 (programmable) relocateable com and seg drivers various instructions display clear, return home, entry mode, duty ratio, display on/off, address shift, pattern shift, dot shift, power control, general ports, electrical volume, ram address, ram data writing voltage boost 2-time, 3-time power on reset function voltage regulator 8-step electrical volume 16-step oscillation circuit external resistor and capacitor required bleeder resistor operating voltage +1.7 to 5.5v c-mos technology (p-sub ) package outline bare chip (for cob) package outline NJU6515c
- 2 - ver.2006-08-22 NJU6515 contents general description 1 features 1 pad alignment 3 pad coordinates 4 block diagram 8 terminal description 9 function description 10 (1) (1) (1) (1) block description block description block description block description 10 10 10 10 (1-1) register 10 (1-2) address count (ac) 10 (1-3) ddram (display data ram) 10 (1-4) character generator rom (cgrom) 11 (1-5) character generator ram (cgram) 12 (1-6) mark ram (mkram) 13 (1-7) clock generator 14 (1-8) lcd driving circuit 14 (1-9) blink control circuit 14 (1-10) oscillator 14 (2) (2) (2) (2) reset circuit reset circuit reset circuit reset circuit 15 15 15 15 initialization by reset 15 ( ( ( (3) 3) 3) 3) instruction instruction instruction instruction 16 16 16 16 (3-1) description of instruction 17 (3-2) display 27 (3-3) initialization by instruction 28 (4) (4) (4) (4) power supply for lcd driving circuit power supply for lcd driving circuit power supply for lcd driving circuit power supply for lcd driving circuit 29 29 29 29 (4-1) regulator/ voltage boost 29 (4-2) electronic volume/internal bleeder resistor 30 (4-3) oscillator frequency and frame frequency 31 (5) (5) (5) (5) interface with cpu interface with cpu interface with cpu interface with cpu 32 32 32 32 absolute maximum rating 34 dc characteristics 35 system interface timing 37 lcd driving voltage waveform 39 application infromation 41 system interface timing ?? ! ????u [^?om?d?{ -3- ver.2006-08-22 NJU6515 pad alignment chip size: 3.45 x 3.25mm chip center: x=0 m, y=0 m pad size : 90 m x 90 m pad pitch: 117.7 m pitch chip thickness: 400 m x y ? ? ? ? ? ~~~~~~~~~~~~~~~~~~~~~~~~? ? ? ? ? ? ? ? ? ? ~~~~~~~~~~~~~~~~~~~~~~~~? ? ? ? ? ? ? ? ? ? ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ? ? ? ? ? ? ? ? ? ? ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ? ? ? ? ? 1 2 3 4 5---------------------------------------------------------------------------------------21 22 23 24 25 73 72 71 70 69 -----------------------------------------------------------------------------53 52 51 50 49 74 75 76 77 78 - - - - - - - - - - - - - - - - - - - - - - 92 93 94 95 96 48 47 46 45 44 ? - - - - - - - - - - - - - - - - - - - - - - - 30 29 28 27 26 top view - 4 - ver.2006-08-22 NJU6515 pad coordinates (1) a mode (sel1="0", sel2="0") chip size 3.45mm x 3.25mm (chip center x= 0m, y=0 m) pad no. terminal x= m y= m pad no. terminal x= m y= m 1 rstout -1412.4 -1452.0 49 seg36 1412.4 1451.0 2 dc -1294.7 -1452.0 50 seg35 1294.7 1451.0 3 sel1 -1177.0 -1452.0 51 seg34 1177.0 1451.0 4 sel2 -1059.3 -1452.0 52 seg33 1059.3 1451.0 5 if1 -941.6 -1452.0 53 seg32 941.6 1451.0 6 if2 -823.9 -1452.0 54 seg31 823.9 1451.0 7 fsel -706.2 -1452.0 55 seg30 706.2 1451.0 8 si -588.5 -1452.0 56 seg29 588.5 1451.0 9 regon -470.8 -1452.0 57 seg28 470.8 1451.0 10 osc1 -353.1 -1452.0 58 seg27 353.1 1451.0 11 vdd -235.4 -1452.0 59 seg26 235.4 1451.0 12 vss -117.7 -1452.0 60 seg25 117.7 1451.0 13 vss 0 -1452.0 61 seg24 0 1451.0 14 vci 117.7 -1452.0 62 seg23 -117.7 1451.0 15 vreg 235.4 -1452.0 63 seg22 -235.4 1451.0 16 c1+ 353.1 -1452.0 64 seg21 -353.1 1451.0 17 c1- 470.8 -1452.0 65 seg20 -470.8 1451.0 18 c2+ 588.5 -1452.0 66 seg19 -588.5 1451.0 19 c2- 706.2 -1452.0 67 seg18 -706.2 1451.0 20 vout 823.9 -1452.0 68 seg17 -823.9 1451.0 21 vlcd1 941.6 -1452.0 69 seg16 -941.6 1451.0 22 vlcd2 1059.3 -1452.0 70 seg15 -1059.3 1451.0 23 v1 1177.0 -1452.0 71 seg14 -1177.0 1451.0 24 v2 1294.7 -1452.0 72 seg13 -1294.7 1451.0 25 v4 1412.4 -1452.0 73 seg12 -1412.4 1451.0 26 seg59 1551.0 -1294.7 74 seg11 -1551.0 1294.7 27 seg58 1551.0 -1177.0 75 seg10 -1551.0 1177.0 28 seg57 1551.0 -1059.3 76 seg9 -1551.0 1059.3 29 seg56 1551.0 -941.6 77 seg8 -1551.0 941.6 30 seg55 1551.0 -823.9 78 seg7 -1551.0 823.9 31 seg54 1551.0 -706.2 79 seg6 -1551.0 706.2 32 seg53 1551.0 -588.5 80 seg5 -1551.0 588.5 33 seg52 1551.0 -470.8 81 seg4 -1551.0 470.8 34 seg51 1551.0 -353.1 82 seg3 -1551.0 353.1 35 seg50 1551.0 -235.4 83 seg2 -1551.0 235.4 36 seg49 1551.0 -117.7 84 seg1 -1551.0 117.7 37 seg48 1551.0 0 85 commk2 -1551.0 0 38 seg47 1551.0 117.7 86 com7 -1551.0 -117.7 39 seg46 1551.0 235.4 87 com6 -1551.0 -235.4 40 seg45 1551.0 353.1 88 com5 -1551.0 -353.1 41 seg44 1551.0 470.8 89 com4 -1551.0 -470.8 42 seg43 1551.0 588.5 90 com3 -1551.0 -588.5 43 seg42 1551.0 706.2 91 com2 -1551.0 -706.2 44 seg41 1551.0 823.9 92 com1 -1551.0 -823.9 45 seg40 1551.0 941.6 93 commk1 -1551.0 -941.6 46 seg39 1551.0 1059.3 94 p1 -1551.0 -1059.3 47 seg38 1551.0 1177.0 95 p2 -1551.0 -1177.0 48 seg37 1551.0 1294.7 96 p3 -1551.0 -1294.7 -5- ver.2006-08-22 NJU6515 (2) b mode (sel1="1", sel2="1") chip size 3.45mm x 3.25mm (chip center x= 0m, y=0 m) pad no. terminal x= m y= m pad no. terminal x= m y= m 1 rstout -1412.4 -1452.0 49 seg24 1412.4 1451.0 2 dc -1294.7 -1452.0 50 seg25 1294.7 1451.0 3 sel1 -1177.0 -1452.0 51 seg26 1177.0 1451.0 4 sel2 -1059.3 -1452.0 52 seg27 1059.3 1451.0 5 if1 -941.6 -1452.0 53 seg28 941.6 1451.0 6 if2 -823.9 -1452.0 54 seg29 823.9 1451.0 7 fsel -706.2 -1452.0 55 seg30 706.2 1451.0 8 si -588.5 -1452.0 56 seg31 588.5 1451.0 9 regon -470.8 -1452.0 57 seg32 470.8 1451.0 10 osc1 -353.1 -1452.0 58 seg33 353.1 1451.0 11 vdd -235.4 -1452.0 59 seg34 235.4 1451.0 12 vss -117.7 -1452.0 60 seg35 117.7 1451.0 13 vss 0 -1452.0 61 seg36 0 1451.0 14 vci 117.7 -1452.0 62 seg37 -117.7 1451.0 15 vreg 235.4 -1452.0 63 seg38 -235.4 1451.0 16 c1+ 353.1 -1452.0 64 seg39 -353.1 1451.0 17 c1- 470.8 -1452.0 65 seg40 -470.8 1451.0 18 c2+ 588.5 -1452.0 66 seg41 -588.5 1451.0 19 c2- 706.2 -1452.0 67 seg42 -706.2 1451.0 20 vout 823.9 -1452.0 68 seg43 -823.9 1451.0 21 vlcd1 941.6 -1452.0 69 seg44 -941.6 1451.0 22 vlcd2 1059.3 -1452.0 70 seg45 -1059.3 1451.0 23 v1 1177.0 -1452.0 71 seg46 -1177.0 1451.0 24 v2 1294.7 -1452.0 72 seg47 -1294.7 1451.0 25 v4 1412.4 -1452.0 73 seg48 -1412.4 1451.0 26 seg1 1551.0 -1294.7 74 seg49 -1551.0 1294.7 27 seg2 1551.0 -1177.0 75 seg50 -1551.0 1177.0 28 seg3 1551.0 -1059.3 76 seg51 -1551.0 1059.3 29 seg4 1551.0 -941.6 77 seg52 -1551.0 941.6 30 seg5 1551.0 -823.9 78 seg53 -1551.0 823.9 31 seg6 1551.0 -706.2 79 seg54 -1551.0 706.2 32 seg7 1551.0 -588.5 80 seg55 -1551.0 588.5 33 seg8 1551.0 -470.8 81 seg56 -1551.0 470.8 34 seg9 1551.0 -353.1 82 seg57 -1551.0 353.1 35 seg10 1551.0 -235.4 83 seg58 -1551.0 235.4 36 seg11 1551.0 -117.7 84 seg59 -1551.0 117.7 37 seg12 1551.0 0 85 commk1 -1551.0 0 38 seg13 1551.0 117.7 86 com1 -1551.0 -117.7 39 seg14 1551.0 235.4 87 com2 -1551.0 -235.4 40 seg15 1551.0 353.1 88 com3 -1551.0 -353.1 41 seg16 1551.0 470.8 89 com4 -1551.0 -470.8 42 seg17 1551.0 588.5 90 com5 -1551.0 -588.5 43 seg18 1551.0 706.2 91 com6 -1551.0 -706.2 44 seg19 1551.0 823.9 92 com7 -1551.0 -823.9 45 seg20 1551.0 941.6 93 commk2 -1551.0 -941.6 46 seg21 1551.0 1059.3 94 p1 -1551.0 -1059.3 47 seg22 1551.0 1177.0 95 p2 -1551.0 -1177.0 48 seg23 1551.0 1294.7 96 p3 -1551.0 -1294.7 - 6 - ver.2006-08-22 NJU6515 (3) c code (sel1="1", sel2="0") chip size 3.45mm x 3.25mm (chip center x= 0m, y=0 m) pad no. terminal x= m y= m pad no. terminal x= m y= m 1 rstout -1412.4 -1452.0 49 seg36 1412.4 1451.0 2 dc -1294.7 -1452.0 50 seg35 1294.7 1451.0 3 sel1 -1177.0 -1452.0 51 seg34 1177.0 1451.0 4 sel2 -1059.3 -1452.0 52 seg33 1059.3 1451.0 5 if1 -941.6 -1452.0 53 seg32 941.6 1451.0 6 if2 -823.9 -1452.0 54 seg31 823.9 1451.0 7 fsel -706.2 -1452.0 55 seg30 706.2 1451.0 8 si -588.5 -1452.0 56 seg29 588.5 1451.0 9 regon -470.8 -1452.0 57 seg28 470.8 1451.0 10 osc1 -353.1 -1452.0 58 seg27 353.1 1451.0 11 vdd -235.4 -1452.0 59 seg26 235.4 1451.0 12 vss -117.7 -1452.0 60 seg25 117.7 1451.0 13 vss 0 -1452.0 61 seg24 0 1451.0 14 vci 117.7 -1452.0 62 seg23 -117.7 1451.0 15 vreg 235.4 -1452.0 63 seg22 -235.4 1451.0 16 c1+ 353.1 -1452.0 64 seg21 -353.1 1451.0 17 c1- 470.8 -1452.0 65 seg20 -470.8 1451.0 18 c2+ 588.5 -1452.0 66 seg19 -588.5 1451.0 19 c2- 706.2 -1452.0 67 seg18 -706.2 1451.0 20 vout 823.9 -1452.0 68 seg17 -823.9 1451.0 21 vlcd1 941.6 -1452.0 69 seg16 -941.6 1451.0 22 vlcd2 1059.3 -1452.0 70 seg15 -1059.3 1451.0 23 v1 1177.0 -1452.0 71 seg14 -1177.0 1451.0 24 v2 1294.7 -1452.0 72 seg13 -1294.7 1451.0 25 v4 1412.4 -1452.0 73 seg12 -1412.4 1451.0 26 seg59 1551.0 -1294.7 74 seg11 -1551.0 1294.7 27 seg58 1551.0 -1177.0 75 seg10 -1551.0 1177.0 28 seg57 1551.0 -1059.3 76 seg9 -1551.0 1059.3 29 seg56 1551.0 -941.6 77 seg8 -1551.0 941.6 30 seg55 1551.0 -823.9 78 seg7 -1551.0 823.9 31 seg54 1551.0 -706.2 79 seg6 -1551.0 706.2 32 seg53 1551.0 -588.5 80 seg5 -1551.0 588.5 33 seg52 1551.0 -470.8 81 seg4 -1551.0 470.8 34 seg51 1551.0 -353.1 82 seg3 -1551.0 353.1 35 seg50 1551.0 -235.4 83 seg2 -1551.0 235.4 36 seg49 1551.0 -117.7 84 seg1 -1551.0 117.7 37 seg48 1551.0 0 85 commk1 -1551.0 0 38 seg47 1551.0 117.7 86 com1 -1551.0 -117.7 39 seg46 1551.0 235.4 87 com2 -1551.0 -235.4 40 seg45 1551.0 353.1 88 com3 -1551.0 -353.1 41 seg44 1551.0 470.8 89 com4 -1551.0 -470.8 42 seg43 1551.0 588.5 90 com5 -1551.0 -588.5 43 seg42 1551.0 706.2 91 com6 -1551.0 -706.2 44 seg41 1551.0 823.9 92 com7 -1551.0 -823.9 45 seg40 1551.0 941.6 93 commk2 -1551.0 -941.6 46 seg39 1551.0 1059.3 94 p1 -1551.0 -1059.3 47 seg38 1551.0 1177.0 95 p2 -1551.0 -1177.0 48 seg37 1551.0 1294.7 96 p3 -1551.0 -1294.7 -7- ver.2006-08-22 NJU6515 4) d mode (sel1="0", sel2="1") chip size 3.45mm x 3.25mm (chip center x= 0m, y=0 m) pad no. terminal x= m y= m pad no. terminal x= m y= m 1 rstout -1412.4 -1452.0 49 seg24 1412.4 1451.0 2 dc -1294.7 -1452.0 50 seg25 1294.7 1451.0 3 sel1 -1177.0 -1452.0 51 seg26 1177.0 1451.0 4 sel2 -1059.3 -1452.0 52 seg27 1059.3 1451.0 5 if1 -941.6 -1452.0 53 seg28 941.6 1451.0 6 if2 -823.9 -1452.0 54 seg29 823.9 1451.0 7 fsel -706.2 -1452.0 55 seg30 706.2 1451.0 8 si -588.5 -1452.0 56 seg31 588.5 1451.0 9 regon -470.8 -1452.0 57 seg32 470.8 1451.0 10 osc1 -353.1 -1452.0 58 seg33 353.1 1451.0 11 vdd -235.4 -1452.0 59 seg34 235.4 1451.0 12 vss -117.7 -1452.0 60 seg35 117.7 1451.0 13 vss 0 -1452.0 61 seg36 0 1451.0 14 vci 117.7 -1452.0 62 seg37 -117.7 1451.0 15 vreg 235.4 -1452.0 63 seg38 -235.4 1451.0 16 c1+ 353.1 -1452.0 64 seg39 -353.1 1451.0 17 c1- 470.8 -1452.0 65 seg40 -470.8 1451.0 18 c2+ 588.5 -1452.0 66 seg41 -588.5 1451.0 19 c2- 706.2 -1452.0 67 seg42 -706.2 1451.0 20 vout 823.9 -1452.0 68 seg43 -823.9 1451.0 21 vlcd1 941.6 -1452.0 69 seg44 -941.6 1451.0 22 vlcd2 1059.3 -1452.0 70 seg45 -1059.3 1451.0 23 v1 1177.0 -1452.0 71 seg46 -1177.0 1451.0 24 v2 1294.7 -1452.0 72 seg47 -1294.7 1451.0 25 v4 1412.4 -1452.0 73 seg48 -1412.4 1451.0 26 seg1 1551.0 -1294.7 74 seg49 -1551.0 1294.7 27 seg2 1551.0 -1177.0 75 seg50 -1551.0 1177.0 28 seg3 1551.0 -1059.3 76 seg51 -1551.0 1059.3 29 seg4 1551.0 -941.6 77 seg52 -1551.0 941.6 30 seg5 1551.0 -823.9 78 seg53 -1551.0 823.9 31 seg6 1551.0 -706.2 79 seg54 -1551.0 706.2 32 seg7 1551.0 -588.5 80 seg55 -1551.0 588.5 33 seg8 1551.0 -470.8 81 seg56 -1551.0 470.8 34 seg9 1551.0 -353.1 82 seg57 -1551.0 353.1 35 seg10 1551.0 -235.4 83 seg58 -1551.0 235.4 36 seg11 1551.0 -117.7 84 seg59 -1551.0 117.7 37 seg12 1551.0 0 85 commk2 -1551.0 0 38 seg13 1551.0 117.7 86 com7 -1551.0 -117.7 39 seg14 1551.0 235.4 87 com6 -1551.0 -235.4 40 seg15 1551.0 353.1 88 com5 -1551.0 -353.1 41 seg16 1551.0 470.8 89 com4 -1551.0 -470.8 42 seg17 1551.0 588.5 90 com3 -1551.0 -588.5 43 seg18 1551.0 706.2 91 com2 -1551.0 -706.2 44 seg19 1551.0 823.9 92 com1 -1551.0 -823.9 45 seg20 1551.0 941.6 93 commk1 -1551.0 -941.6 46 seg21 1551.0 1059.3 94 p1 -1551.0 -1059.3 47 seg22 1551.0 1177.0 95 p2 -1551.0 -1177.0 48 seg23 1551.0 1294.7 96 p3 -1551.0 -1294.7 - 8 - ver.2006-08-22 NJU6515 block diagram reset circuit serial interface oscillator data register (dr) instruction register (ir) instruction decoder ( id ) address counter display data ram (ddram) 11x8-bit icon display ram (mk ram) 118 bits character generator rom (cgrom) 6,720 bits character generator ram (cgram) 77x5 bits timing generator blink controller 9 bits shift register com drive r parallel to serial converter / scroll circuit voltage converter / regulator vlcd vlcd sel1 se l 2 c1 c1 c2 c2 d c si osc1 vout com1~ com7, comm1, comm2 seg1~ seg59 vdd v1 if1 p1~ p3 if2 v2 (v3) v4 vss vlcd v1 v2 (v3) v4 vss 59 bits latch circuit seg driver 59 bits shift register output port register output port driver vci re gon fsel v re g rstout -9- ver.2006-08-22 NJU6515 terminal description no. symbol i/o function 11 v dd - power supply terminal v dd =1.7~5.5v 12,13 v ss - ground terminals v ss =0v 21, 22, 23,24, 25 vlcd1, vlcd2, v1, v2, v4 - lcd driving voltage supply terminals 16,17, 18,19 c1+, c1- c2+, c2- - capacitor connecting terminals for voltage boost. 14 v ci - voltage boost input terminal. 20 v out output voltage boost output terminal. 2 dc input voltage boost selection terminal. "l": 2-time "h": 3-time 10 osc1 input resistor and capacitor connecting terminal for oscillation circuit. (or external clock input terminal.) 26~84 seg1~ seg59 output segment driver output terminals. 86~92 com1~ com7 output common driver output terminals. 85,93 commk1, commk2 output common driver output terminals for icons 94~96 p1~p3 output general purpose ports 8 si input serial data input terminal 5,6 if1, if2 input cycle time select terminals 9 regon input regulator on/off terminal "l": off "h": on 15 vreg output regulator output terminal 7 fsel input internal oscillator/external clock select terminal "l": internal oscillator "h": external clock 1 rstout output reset signal output terminal 3 sel1 input select com drivers scan direction "l": com1 com7, commk1, commk2 "h": commk2, commk1, com7 com1 4 sel2 input set seg drivers output sequence "l": seg1 seg59 "h": seg59 seg1 dc, if1, if2, regon, fsel, sel1, sel2 terminals should be fixed ahead - 10 - ver.2006-08-22 NJU6515 function description (1) block description (1-1) register NJU6515 has one 8-bit instruction register (ir) and one 8-bit data register (dr), ir is used to hold instructions like display clear, etc. dr is used to save the cpu-sending data temporally which will be eventually written to ddram, cgram, mkram. table 1 ? register select d11 d10 d9 d8 operation 0 0 0 0 instruction to ir, and then executed 1 1 0 0 set up ram address 0 0 1 1 display data to dr, and then to ram (1-2) address count (ac) ac is used to count ram address. after the ram data writing, the ac will increase +1 or ?1 automatically. (1-3) ddram (display data ram) the size of ddram is 8x11 bits. one 8-bit data represents a code of a character. so total 11 character codes can be saved on ddram (a 8-bit blank area is reserved for display scroll) the relationship between ddram address and display location on panel is as below, and the ddram address is in hex. exp. ddram address is "08" ac ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 0 0 0 0 1 0 0 0 1 2 3 4 5 6 7 8 9 10 display location on panel 00 01 02 03 04 05 06 07 08 09 0a dd ram address (hexadecimal) a ddram blank area for display scroll for shift display, the ddram address moves like below. [left shift] (00) 01 02 03 04 05 06 07 08 09 0a 00 [right shift] 0a 00 01 02 03 04 05 06 07 08 09 (0a) hexadecimal 08 -11- ver.2006-08-22 NJU6515 (1-4) character generator rom (cgrom) cgrom has 192 patterns of 5x7-dot characters. every pattern can be located by an 8-bit ddram data. the relationship between an 8-bit code and a pattern is shown on the following table 2. furthermore, if other than the following patters are requested, please contact njrc for customized rom. even with customized pattern, (20) h need to be space, and (0 ? ) h , (1 ? ) h , (8 ? ) h , (9 ? ) h shall be invalid. table 2 code and pattern (rom version 06) - 12 - ver.2006-08-22 NJU6515 (1-5) character generator ram (cgram) cgram is used for creating patterns not included on cgrom, and totally 11 5x7-dot patterns can be written on cgram. ddram data (00) h ? (0a) h is reserved as codes of cgram patterns. the relationship among ddram data, cgram address and patter data is shown on table 3 table 3 cgram address and ddram data and patterns cgram data ddram data cgram address cgram data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 4 3 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 1 1 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 1 ? ? ? ? ? pattern (1) 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 0 0 0 1 0 1 0 1 0 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 0 0 1 0 0 0 0 1 0 0 ? ? ? ? ? pattern (2) 0 0 0 0 0 1 0 0 0 0 1 0 1 0 1 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 pattern (11) ? ? ? ? ? ? ? ? invalid ? note 1. 0~3 bits of ddram data is corresponding with 3~6 bits of cgram address. 2. 0~2 bits of cgram is the line address for every cgram pattern, and the 8 th line is invalid. if cgram data is input continually, the 8 th address of every pattern will be automatically over-passed. 3. cgram data has 5 bits, and bit 4 data is the left side of the pattern. 4. ddram data is used to specify either the cgrom patterns or cgram patters, for cgram pattern display, the upper 4 bits (4~7) of ddram data shall be ?0?. 5. if cg ram data ="1", corresponding pixel on, if data =0", pixel off. 6. after power on, because cgram data is indefinitive, please write data into cgram before display on. -13- ver.2006-08-22 NJU6515 (1-6) mark ram (mkram) the mkram can store as much as 118 data for icon display. only when db1 and db2 bits of ?display on/off? instruction are set to 1, icon display is effective. when mkram data=1, mark display on, data=0, mark display off. the relationship between the address of mkram and marks is shown on table 4 table 4 mkram address and mark number mark number mkram address (commk1:e0 h ? e9 h ) (commk2:ea h ? f3 h ) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1110 ? 0000 e0 h * * 1 2 3 4 5 6 1110 ? 0001 e1 h * * 7 8 9 10 11 12 1110 ? 0010 e2 h * * 13 14 15 16 17 18 1110 ? 0011 e3 h * * 19 20 21 22 23 24 1110 ? 0100 e4 h * * 25 26 27 28 29 30 1110 ? 0101 e5 h * * 31 32 33 34 35 36 1110 ? 0110 e6 h * * 37 38 39 40 41 42 1110 ? 0111 e7 h * * 43 44 45 46 47 48 1110 ? 1000 e8 h * * 49 50 51 52 53 54 1110 ? 1001 e9 h * * 55 56 57 58 59 * 1110 ? 1010 ea h * * 60 61 62 63 64 65 1110 ? 1011 eb h * * 66 67 68 69 70 71 1110 ? 1100 ec h * * 72 73 74 75 76 77 1110 ? 1101 ed h * * 78 79 80 81 82 83 1110 ? 1110 ee h * * 84 85 86 87 88 89 1110 ? 1111 ef h * * 90 91 92 93 94 95 1111 ? 0000 f0 h * * 96 97 98 99 100 101 1111 ? 0001 f1 h * * 102 103 104 105 106 107 1111 ? 0010 f2 h * * 108 109 110 111 112 113 1111 ? 0011 f3 h * * 114 115 116 117 118 * * (don?t care) note) the mkram is not initialized with power on. if mark display is used, write data to mkram first. mark display is not affected by ?pattern shift? instruction. when duty=1/8, the range of mkram address should be set between e0 h ~e9 h. commk1 com1 com2 com3 com4 com5 com6 com7 commk2 seg 1 2 3 4 5 6 7 8 9 10 11 12 131415 161718 55 56 57 58 59 60 118 1 59 - 14 - ver.2006-08-22 NJU6515 (1-7) clock generator the clock generator outputs timing signal for ddram, mkram, cgram and cgrom control. the ram data readout timing is independent from cpu access. for this reason, even during ddram data writing, except pixels which the corresponding data being rewritten, no blink can be observed. (1-8) lcd driving circuit the circuit consists of 9 com drivers and 59 seg drivers. the 59 bits display data will be latched after read in the shift register, the latched data will control the seg drivers to output lcd driving bias voltage. note) lcd display the 6n (n=1,2,3?) seg drivers will output ?l? during cgrom/cgram patters display. when the ?smooth scroll? function is used, the blank lines will shift together with the patterns, but for mark display, the 6n seg drivers will always output signals according to mkram data. (1-9) blink control circuit the circuit is used to control the display blink. when the ?blink control? is on, the character, which address is specified by ac, will blink. for example, if the ac = (04) h , the 5th character will blink. ac 7 ac 6 ac 5 ac 4 ac 3 ac 2 ac 1 ac 0 ac 0 0 0 0 0 1 0 0 1 ; 2 3 4 ? 5 6 7 8 9 10 display location 00 01 02 03 04 05 06 07 08 09 ddram address (16 hex) note) if the address of cgram or mkram is set in ac, even when the blink function is on, because no display location is corresponding with a cgram/mkram address, there is no blink character on the panel. so please set the blink function off in this case. (1-10) oscillator the oscillation circuit use external capacitor and resistor to generate clock. if the oscillator is used, fix fsel to ?l?, when external clock is used, fix fsel to ?h? and input clock from osc1 pin. blink character commk1 com1 com2 com3 com4 com5 com6 com7 commk2 seg 1 2 3 4 5 6 7 8 9 10 11 12 131415 161718 55 56 57 58 59 a a a a the 6n (n=1,2,3?) seg drivers outputs ?l? for cgrom/ram p attern dis p la y . n o 60 t h seg drive r the seg drivers output signals basing on mkram data during commk scan -15- ver.2006-08-22 NJU6515 (2) reset circuit initialization by reset the ic is initialized when power on. the following instruction will be executed during initialization. please refer to (5) [interface with cpu] for reset timing. display clear entry mode duty display on/off power control general ports electronic volume dot shift note) if the power supply could not meet the conditions stated in [the power supply startup], the reset circuit may be malfunction. d =0 display off m =0 mark off b =0 blink off dt =1 1/8duty v =0 voltage boost off re2, 1, 0 =0, 0, 0 p3, 2, 1 =0, 0, 0 general ports of f ev3, 2, 1, 0 =0, 0, 0, 0 ds2, 1, 0 =0, 0, 0 dot shift = 0 i/d =1 +1(increment) s =0 no shift 20h is written into ddram, ac is se t to 00h. - 16 - ver.2006-08-22 NJU6515 (3) instruction the ic has the instruction register (ir) and the data register (dr). the data from cpu will be stored in these registers first, and then executed internally. the msb of data will be written in first. the ram address shall be setup before ram data writing. table 5 instruction list start condition instruction code instruction db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 description a maker test 1 0 10 0 0 0000000000only for maker using b display clear 1 0 1 0 0 0 0 0 0 0 0 1 * * * * the ddram address 00h is set into ac by this instruction. c return home 1 0 1 0 0 0 0 0 0 0 1 0 * * * * the ddram address 00h is set into ac, the shifted characters return to its initial p lace. no change of ddram data. d entry mode 1 0 1 0 0 0 0 0 0 0 1 1 * * i/d s set address increment and shift direction. e duty ratio 1 0 1 0 0 0 0 0 0 1 0 0 * * * dt set duty ratio to 1/8 or 1/9. f display on/off 1 0 1 0 0 0 0 0 0 1 0 1 * d m b display on/off (d), mark on/off (m), blink function on/off. g address shift 1 0 1 0 0 0 0 0 0 1 1 0 * * * ar l address increment or decrement even without data writing. h pattern shift 1 0 1 0 0 0 0 0 0 1 1 1 * * * dr l displayed character shift to the right or left i dot shift 1 0 1 0 0 0 0 0 1 0 0 0 * ds 2 ds 1 ds 0 0~5 bits dot shift. combined with pattern shift, smooth scroll can be realized. j power control 1 0 1 0 0 0 0 0 1 0 0 1 v re 2 re 1 re 0 voltage boost on/off, and set regulator. k general ports 1 0 1 0 0 0 0 0 1 0 1 0 * p3 p2 p1 set general ports (p3~p1) l electronic vo l u m e 1 0 1 0 0 0 0 0 1 0 1 1 ev 3 ev 2 ev 1 ev 0 m ram address 1 0 1 0 1 1 0 0 address set the address of ddram, cgram, mkram write data (ddram) * * * write data (cgram) n ram data writing 1 0 1 0 0 0 1 1 * * write data (mkram) i/d=1: increment i/d=0: decrement s=1: pattern shift dt=1:1/8duty dt=0:1/9duty z d=1: display on d=0: display off m=1: mark on m=0: mark off b=1: blink on b=0:blink off arl=1: address+1 arl=0: address -1 drl=1: right shift drl=0: left shift dsx: dot shift v=1: boost on v=0: boost off rex: setting regulator px: general ports setting evx: contrast ratio setting *: don't care *1) the execution time of power control instruction means the time between the start of instruction processing and the power circuit reacting. practically, power system need more time to stabilize. *2) do not input data other than the above shown. -17- ver.2006-08-22 NJU6515 (3-1) description of instruction (a) maker test db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 do not use this instruction. (b) display clear db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 1 0 0 0 0 0 0 0 0 1 * * * * the space font (20)h is written to all the bits of ddram, and the ac is set to (00)h, the id bit of ?entry mode? is sent to 1 (increment), ?pattern shift? and ?dot shift? functions are off. the data of mk/cgram is unchanged. note) for the customized rom, the pattern of (20)h shall be space code too. (c) return home db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 1 0 0 0 0 0 0 0 1 0 * * * * by this instruction, the ac is set to (00)h, i/d of ?entry mode? is set to ?1?, ?pattern shift? and ?dot shift? are initialized. ddram data is not changed, if blink function used, the first character on panel will blink. - 18 - ver.2006-08-22 NJU6515 (d) entry mode db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 1 0 0 0 0 0 0 0 1 1 * * i/d s the address increment direction and pattern shift direction are set by this instruction. if data is continually written to the cgram, invalid address will be automatically over passed. i/d function 1 the address of the ddram, cgram and mkram increase 1. 0 the address of the ddram, cgram and mk ram decrease 1. s function 1 if i/d=1, displayed patterns move to the left, if i/d=0, display patterns move to the right. during data writing, ?pattern shift? is invalid. 0 no pattern shift (e) duty ratio db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 1 0 0 0 0 0 0 1 0 0 * * * dt if duty ratio=1/9, both commk1 and commk2 drivers can be used, if duty ratio=1/8, only one commk driver can be used. dt function 1 1/8, max. 59 marks 0 1/9, max.118 marks when change duty ratio from 1/9 to 1/8, the mkram address need to be revised and rewrite the data for mkram. -19- ver.2006-08-22 NJU6515 (f) display on/off db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 1 0 0 0 0 0 0 1 0 1 * d m b d function 1 display on 0 display off, ddram data is remained, when set d=1 again, remained data will be shown as before. during display off, all com or seg drivers output ?l?. m function 1 mark display on (if d=0, mark display off) 0 mark display off b function 1 the pattern which address is stored at ac will blink. the blink function is realized by alternately display a font and all 5x7 dot in black at a frequency of 2.5hz (400.16ms, f osc =380khz, 1/9 duty ratio), or, 2.8hz(355.71ms, f osc =380khz, 1/8 duty ratio). 0 no blink (g) address shift db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 1 0 0 0 0 0 0 1 1 0 * * * arl the address of ddram/cgram/mkram shifts to the right or left even without data writing. arl function 1 ac+1 0 ac-1 if the cgram/mkram address is selected, the execution of ?address shift? will lead to the ddram. if want to write data to ddram after ?address shift?, it is necessary to set up ddram address. f j j j f j f f f j j f f f j j f f f j j j j j j j f f f j j f f f j alternate display (2) blink display j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j f j j j f j f f f j j f f f j j f f f j j j j j j j f f f j j f f f j 5x7 dot (1) normal display - 20 - ver.2006-08-22 NJU6515 (h) pattern shift db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 1 0 0 0 0 0 0 1 1 1 * * * drl without data rewriting, the displayed pattern can move to the left or right by this instruction, but ac address will not change. drl function 1 displayed patterns move to the right 0 displayed patterns move to the left (i) dot shift db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 1 0 0 0 0 0 1 0 0 0 * ds2 ds1 ds0 using this instruction with ?pattern shift?, smooth scroll can be realized. ds2 ds1 ds0 function 0 0 0 0 dot shift (no shift) 0 0 1 1 dot shift to the left 0 1 0 2 dots shift to the left 0 1 1 3 dots shift to the left 1 0 0 4 dots shift to the left 1 0 1 5 dots shift to the left 1 1 0 1 1 1 invalid note1) if using smooth scroll mode, set i/d=1, s=0 of ?entry mode?. note2) ?dot shift? is reset to ?0 dot shift? when ?pattern shift? is executed. note3) displayed marks do not shift. -21- ver.2006-08-22 NJU6515 ? smooth scroll by setting ds2~ds0 of ?dot shift?, one of the 3 scroll patters can be selected. (1dot smooth scroll, 2-dot smooth scroll, 3-dot smooth scroll) 1-dot smooth scroll 2-dot smooth scroll shifted dot shifted dot ds2 ds1 ds0 ds2 ds1 ds0 1dot shift 0 0 1 2dot shift 0 1 0 2dot shift 0 1 0 4dot shift 1 0 0 3dot shift 0 1 1 pattern shift dot shift="0" 4dot shift 1 0 0 5dot shift 1 0 1 2dot shift 0 1 0 pattern shift dot shift="0" 4dot shift 1 0 0 pattern shift dot shift="0" 1dot shift 0 0 1 2dot shift 0 1 0 3dot shift 0 1 1 3-dot smooth scroll 4dot shift 1 0 0 shifted dot 5dot shift 1 0 1 ds2 ds1 ds0 3dot shift 0 1 1 pattern shift dot shift="0" pattern shift dot shift="0" 3dot shift 0 1 1 pattern shift dot shift="0" - 22 - ver.2006-08-22 NJU6515 ? 2-dot smooth scroll the displayed pattern and ddram address will change like below under 2-dot smooth scroll. power on write pattern data to (00~09)h of ddram display on/off set up (0a)h of ddram write pattern data to ( 0a ) h 2 dots shifted 4 dots shifted pattern shift 2 dots shifted 4 dots shifted pattern shifted write pattern data to ( 01 ) h ? dis p la y ed patter n ? ? ddram address ? 00 01 02 07 08 09 0a 1st p attern 2 3 8 9 10 ddram address which is set up in ac ddram address for scroll 00 01 02 07 08 09 0a 00 01 02 07 08 09 0a 00 01 02 07 08 09 0a 01 02 03 08 09 0a 00 01 02 03 08 09 0a 00 01 02 03 08 09 0a 00 02 03 04 09 0a 00 01 write pattern data to (00)h -23- ver.2006-08-22 NJU6515 ? 3-dot smooth scroll the displayed pattern and ddram address will change like below under 3-dot smooth scroll. write pattern data to (00~09)h of ddram display on/off set up (0a)h of ddram 3 dots shifted pattern shifted 3 dots shifted pattern shifted ? displayed pattern ? ? ddram address ? 00 01 02 07 08 09 0a 1 ; 2 3 8 9 10 00 01 02 07 08 09 0a 00 01 02 07 08 09 0a 01 02 03 08 09 0a 00 01 02 03 08 09 0a 00 02 03 04 09 0a 00 01 power on write pattern data to ( 0a ) h write pattern data to (00)h write pattern data to ( 01 ) h ddram address in ac ddram address for scroll - 24 - ver.2006-08-22 NJU6515 (j) power control db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 1 0 0 0 0 0 1 0 0 1 v re2 re1 re0 the voltage boost and the regulator are controlled by this instruction. the regulator output can be selected from 8 steps. v function 1 voltage boost on 0 voltage boost off re2 re1 re0 output of the regulator (vreg pin) 0 0 0 1.9v (default) 0 0 1 2.0v 0 1 0 2.1v 0 1 1 2.2v 1 0 0 2.3v 1 0 1 2.4v 1 1 0 2.5v 1 1 1 2.6v (k) general ports db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 1 0 0 0 0 0 1 0 1 0 * p3 p2 p1 outputs from the general ports (p3, p2, p1) are controlled by the instruction, the general ports can be used to control led. the outputs are initialized to ?l?. px general ports 1 "h" 0 "l" (l) electronic volume db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 1 0 0 0 0 0 1 0 1 1 ev3 ev2 ev1 ev0 the contrast of lcd can be adjusted by setting the value of ev3-0, the lcd driving voltage vlcd can be selected from 16 steps. if not using this function, set (ev3, ev2, ev1, ev0) = (0,0,0,0). ev3 ev2 ev1 ev0 vlcd vlcd=vlcd2-vss 0 0 0 0 low 0 0 0 1 : 0 0 1 0 : : : : : : : : : : : 1 1 0 1 : 1 1 1 0 : 1 1 1 1 high -25- ver.2006-08-22 NJU6515 (m) ram address db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 1 0 1 1 0 0 a a a a a a a a if db11~db8 =(1,1,0,0) to, and db7~db0 will be the ram address, and this address is also informed to ac (address count). dd ram: (00)h ~ (0a)h cg ram: (80)h ~ (d6)h mk ram: (e0)h ~ (f3)h --- dd ram: 8-bit data for one address --- cg ram: 5-bit data for one address --- mk ram: 6-bit data for one address * invalid area. lsb is invalid at (e9)h and (f3)h of mkram area ( ? ). 1234567 0 0000 ******* 1 0001 ******* 2 0010 ******* 3 0011 ******* 4 0100 ******* 5 0101 ******* 6 0110 ******* 7 0111 ******* 8 1000 ******* 9 1001 ******* a 1010 ******* b 1011 ******* c 1100 ******* d 1101 ******* e 1110 ******* f 1111 ******* lower 4bit 0000 0 * * * * * 0001 0010 0011 0100 0101 0110 0111 8 1000 1110 1111 9abc upper 4bit de f 1001 1010 1011 1100 1101 ** (00)h (02)h *** * (01)h * * * * * ****** * * * * * * * * ? (0a)h * * dd ram address cg ram address mk ram address * * * * commk2 commk2 commk1 (03)h (05)h (07)h (09)h (04)h (06)h (08)h - 26 - ver.2006-08-22 NJU6515 (n) ram data writing -dd ram db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 1 0 0 0 1 1 d d d d d d d d -cg ram db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 1 0 0 0 1 1 * * * d d d d d -mk ram db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 1 0 0 0 1 1 * * d d d d d d write (0,0,1,1) to db11~db8, and db7~db0 will be stored in ddram/cgram/mkram. and it is 8 bits for ddram, 5 bits for cgram, 6 bits for mkram. after data writing, the address will automatically increase/decrease 1. the invalid address of cgram will be automatically over passed during writing data to cgram ~ increment -ddram : (00)h (01)h --- (0a)h (00)h -cgram : (80)h (81)h --- (d6)h (80)h -mkram(1/8duty) : (e0)h (e1)h --- (e9)h (e0)h -mkram(1/9duty) : (e0)h (e1)h --- (f3)h (e0)h ~ decrement -ddram : (0a)h (09)h --- (00)h (0a)h -cgram : (d6)h (d5)h --- (80)h (d6)h -mkram(1/8duty) : (e9)h (e8)h --- (e0)h (e9)h -mkram(1/9duty) : (f3)h (f2)h --- (e0)h (f3)h -27- ver.2006-08-22 NJU6515 (3-2) display the ddram is used to store 11 patterns? code. using ?pattern shift? instruction, scroll display can be realized. the ?pattern shift? instruction only changes the patterns? display location. the data stored on ddram is not changed. using ?return home? instruction, the initial pattern array can be restored. note) if using internal reset circuit, the power supply shall meet the condition of the reset circuit. if power supply can not meet the request, please use instruction to reset. table 6 display example (using internal reset) no. instruction display function 1 power on initialized, no display 2 power control db11~db0 (0000 1001 1xxx) voltage boost on 3 display control (0000 0101 0101) display on, blink on, space pattern displayed 4 entry mode (0000 0011 0010) address increment mode during ddram / cgram access. no pattern shift 5 write code of n to ddram (0011 0100 1110) ac= (01)h 6 write code of e to ddram (0011 0100 0101) ac= (02)h 7 write code of w to ddram (0011 0101 0111) ac= (03)h 8 entry mode (0000 0011 0011) pattern shift on 9 write code of space to ddram (0011 0010 0000) ac= (03)h 10 write code of j to ddram (0011 0100 1010) ac= (03)h --- ----- ---- --- ----- --- 11 --- ----- --- 12 write code of n to ddram (0011 0100 1110) ac= (03)h 13 address shift (0000 0110 0000) ac=(02)h left shift of address 14 address shift (0000 0110 0000) ac=(01)h left shift of address 15 write code of a to ddram (0011 0100 0001) revise ?o? to ?a?, ac=(01)h left shift of address { 16 return home (0000 0010 0000) ac=(00)h, the patterns relocated according to input sequence n n e n ew n ew ew w j n pon new j pon new j pon new j an new ja n ew japan - 28 - ver.2006-08-22 NJU6515 (3-3) initialization by instruction if internal reset circuit cannot operate correctly, initialization can be realized by instruction. power on ? db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 0 1 v re2 re1 re0 regulator / voltage boost setting 0 0 0 0 1 0 1 1 ev3 ev2 ev1 ev0 electronic volume 0 0 0 0 0 0 0 1 * * * * display clear 0 0 0 0 0 0 1 1 * * i/d s entry mode 0 0 0 0 0 1 0 0 * * * dt duty ratio 0 0 0 0 0 1 0 1 * d m b display, mark, blink on/off 0 0 0 0 1 0 1 0 * p3 p2 p1 general ports 0 0 0 0 1 0 0 0 * ds2 ds1 ds0 dot shift ? initialization over -29- ver.2006-08-22 NJU6515 (4) power supply for lcd driving circuit (4-1) regulator/ voltage boost the regulator is built in, and input voltage from vci is regulated and the output voltage from regulator can be selected by setting re bits of ?power control? instruction, this output voltage is supplied to the voltage boost. by setting regon pin, the voltage regulator can be turned on or off. regon = "h": regulator on. (the regulator output voltage is supplied to the voltage boost via vreg pin.) regon = "l": regulator off (the input voltage via vci pin is directly supplied to the voltage boost.) note) be sure not let the vout over 5.5v. < x2 boost > if vci ? 2.7v, let the regulator off, and supply vci directly to the voltage boost. if vci ? 3.3v, use the regulator to step down the vci and then supply to the voltage boost. if 2.7v - 30 - ver.2006-08-22 NJU6515 (4-2) electronic volume/internal bleeder resistor the ?electronic volume? is used to optimize the lcd contrast ratio by adjusting the vlcd. by setting the 4-bit electronic volume register, the vlcd can select from 16 levels. 37.5k (evr=max) vlcd2 v1 v2 (v3) v4 vss 40k 40k 40k 40k vlcd v1 v2 (v3) v4 vss vlcd electronic volume (16 steps) vlcd1 -31- ver.2006-08-22 NJU6515 (4-3) oscillator frequency and frame frequency when the oscillator frequency is 380khz, the frame frequency is like below. (1clock = 1/380000=2.631 s) <1/8 duty> <1/9 duty> <1/9 duty> <1/8 duty> 1 frame = 2.631( s) x 528 x 9 = 12.503(ms) 1 frame = 2.631( s) x 528 x 8 = 11.113(ms) frame frequency = 1/12.503(ms) = 79.984(hz) frame frequency = 1/11.113(ms) = 89.982(hz) * power on/off ? ? using the regulator/the voltage boost power on: input vci after vdd on. start up the regulator and supply the vreg to the voltage boot until it is stabilized. after the boost stabilized, enable the display on. power off: after display off, stop the operation of the voltage boost, and then let vci down, finally vdd down. ? not using the regulator and the voltage boost, input vlcd directly from outside. power on: first vdd on, then input vlcd. power off: first display off, then vlcd down, last vdd down. vlcd v1 v2 (v3) v4 vss 1 23 4 --- 7 mk1 1 2 3 4 --- 7 mk1 1 2 528 clocks vlcd v1 v2 (v3) v4 vss 1 23 4 --- 7 mk1 mk2 1234 --- 7 mk1 mk2 1 2 528 clocks - 32 - ver.2006-08-22 NJU6515 (5) interface with cpu the 16-bit per word serial data is transferred via one line. according to the time length of ?h? or ?l? level of the signals, the data is interrupted as ?1? or ?0?. after setting a fixed waiting time, if the first 4 msb is ?1010?(a start signal), the rest 12 bit will be read in as the instruction/address/display data. the cycle time of one bit can be selected from 4 levels according to the different combinations of if1 and if2 pin (refer to the ?bus timing characteristics?). after the power supply reaching 1.7v, keep si at ?l? level at least t microseconds before the data input. t=0.1ms(typ.) + 138t clk + 645t clk note) t is valid when the ?dc characteristics? determined resistance and capacitance for oscillator are used. namely the resistance =51kohm, capacitance=120pf. the t w is different from t w1 , t w2 and only used for initialization. ~ data input ~ data interruption ("1" / "0") si data="1" data "1" time length serial clock/ cycle time data="0" time length si data="0" initialization time ( t ) startup time of oscillator 0.1ms(typ.) reset time 138t clk waiting time t w =645t clk 1 s t data vdd si t clk = 1/f osc -33- ver.2006-08-22 NJU6515 ~ example of data input the instruction is executed during the wait time, and ready to accept of the next instruction. if more than16 bits data inputted, only the msb 16 bits are valid. if less than 15 bits data inputted, if less than 15 bits is inputted during wait time, the interface is reset and this 15-bit data become invalid. the instruction data is read in during the 16 th cycle time and then start to be executed. wai t 1 0 1 0 (12-bit) t w1 or t w2 start condition instruction / display data wai t 1 0 1 0 (12-bit) t w1 or t w2 start condition db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db15 db14 db13 db12 db11 db10 db9 db15, 14, 13 --- 1, 0 inputted in turn after wait time si waveform 1 01 0 1 1 0010010111 0/1 judgment 1 0 1 0 0 0 1 1 st word=address"1001 0111" 2 n d word data read in / instruction to be execute d instruction executed interface reset / ready fo r accepting the next instruction - 34 - ver.2006-08-22 NJU6515 absolute maximum rating (ta=25 c) parameter symbol condition rating unit power supply (1) vdd -0.3 ~ +7.0 v power supply (2) vlcd1 -0.3 ~ +7.0 v power supply (3) vlcd2 -0.3 ~ +7.0 v power supply (4) vci vss (0v) -0.3 ~ +7.0 v input voltage vt -0.3 ~ vdd+0.3 v operating temperature topr -40 ~ +85 c storage temperature tstg -55 ~ +125 c note1) stress beyond those listed under ?absolute maximum rating? may cause permanent damage to the device. note 2) it is necessary to meet the conditions of vdd>vss, vci>vss and vss=0v, and vlcd1 shall be applied after vdd on. note 3) to stabilize the device operation, it is better to insert decoupling capacitors between vdd-vss, vci-vss, and vlcd1,2-vss. -35- ver.2006-08-22 NJU6515 dc characteristics (vdd=1.7 ~ 3.6v, ta=-40 ~ +85 c) parameter symbol conditions min typ max unit note power supply v dd vdd pin 1.7 - 5.5 v v ih 0.8v dd - v dd v input voltage v il 0 - 0.2v dd v 4 si pin, v dd =2v - 0.5 - v hysteresis voltage v h si pin, v dd =3v - 0.6 - v driver on resistance (com) r com i d =1 a, v lcd1 =v lcd2 =3v/5.5v - - 20 k ? driver on resistance (seg) r seg i d =1 a, v lcd1 =v lcd2 =3v/5.5v - - 30 k ? 5 input leak current i li v in =0v ~ v dd -1 - 1 a 6 i dd1 - 55 100 power supply current (1) ici 1 v dd =2v, vci=3.3v, display on, x2 boost (dc=v ss ), si=v ss regulator on: (re2, 1, 0)=(000) v in =0v or 2v, ta=25 ? , f osc within the range, if2=if1=v ss - 55 100 a 7 i dd2 - 50 100 power supply current (2) ici 2 v dd =1.8v, vci=1.8v, display on, x3 boost (dc=v dd ), si=v ss regulator off: (re2, 1, 0)=(000) v in =0v or 1.8v, ta=25 ? , f osc within the range, if2=if1=v ss - 110 170 a 7 power supply current (3) i lcd1 v dd =3v, vci=3.3v, display on, si=v ss , v in =0v or 3v, ta=25 ? , f osc within the range. - 30 60 a 7 v oh v dd =2v, i o =0.4ma, p3~p1 pins v dd -0.4 - - v output voltage v ol v dd =2v, i o =0.4ma, p3~p1 pins - - 0.4 v lcd operation voltage v lcd1 v lcd1 pin, v dd =3v, v lcd >v dd 3.0 - 5.5 v v 1 3.45 3.75 4.05 v 2 (v 3 ) 2.2 2.5 2.8 lcd bias voltage v 4 ta=25 ? v dd =3v, v lcd1 = v lcd2 =5v, v ss =0v 0.95 1.25 1.55 v bleeder resistance r b v lcd2 -v ss =5v, ta=25 ? , r b =(v lcd2 -v ss )/ib, evr=(1111), ib: current of bleeder resistor, ta=25 ? 130 160 190 k oscillator frequency f osc v dd =3v,ta=25 ? , fsel=v ss , r=51k , c=120pf 342 380 418 khz external clock f cp input to osc1 pin, fsel=v dd 342 380 418 khz duty of external clock duty input to osc1 pin, fsel=v dd 45 50 55 ? (re2, 1, 0)=(000) 1.80 1.90 2.00 (re2, 1, 0)=(001) 1.90 2.00 2.1 (re2, 1, 0)=(010) 1.99 2.10 2.21 (re2, 1, 0)=(011) 2.09 2.20 2.31 (re2, 1, 0)=(100) 2.18 2.30 2.42 (re2, 1, 0)=(101) 2.28 2.40 2.52 (re2, 1, 0)=(110) 2.37 2.50 2.63 output voltage v reg vci=3.3v ta=25 c (re2, 1, 0)=(111) 2.47 2.60 2.73 v8 difference between input and output voltage ? v io i out =1ma, ta=25 ? - 0.2 0.6 v 8 input voltage vci vci pin, regulator on, ta=25 ? - - 5.5 v 8 regulator current i reg vci=3.3v, regulator on: (re2,1,0)=(000), ta=25 ? , vci pin. v out open, v lcd1 =5v, boost off, 1 f capacitor between v reg -v ss . - 6 20 a regulator load stability ? v reg vci=3.3v, i out =1~5ma, ta=25 ? - - 200 mv 8 vci=2.7v,regon=0v,dc=0(x2 boost), ta=25 c 5.0 5.3 - v 9 boost output voltage v out vci=1.8v,regon=0v, dc=1(x3 boost), ta=25 c 5.0 5.3 - - 36 - ver.2006-08-22 NJU6515 note 4) apply to osc1, sel1, sel2, regon, if2, if1, dc and si pins note 5) the resistance between each com/seg driver and vlcd/vss/v1/v2/v4 pins when id current pass through. note 6) apply to si, sel1, sel2, regon, if2, if1, dc and fsel pins. note 7) idd: vdd pin, vout and vlcd1 connected, boost on, evr=( 1111). ici: vci pin, vout and vlcd1 connected, boost on, evr=(1111). ilcd1: vlcd1 pin, vout open, vlcd1=5v, boost off, evr=( 1111). *connect 1 f capacitor between vreg-vss, c1-~c1+, c2-~c2+, vout-vss. note 8) connect 1 f capacitors between vci-vss, vreg-vss. the min. input voltage is limited by the output voltage and ? v io . note 9) vout and vlcd1 connected, connect 1 f capacitors between vreg-vss, c1-~c1+, c2-~c2+, vout-vss. note 10) if vin is defined in the conditions, it applies to the input pins which is not specified in the conditions. -37- ver.2006-08-22 NJU6515 system interface timing ? 1-line serial interface (vdd=1.7 ~ 3.6v, vss=0v, ta=-40 ~ +85 c, fosc=380khz) parameter symbol min typ max unit if2 if1 wait time 1 *1 t w1 600t clk - - s - - wait time 2 *2 t w2 280t clk - - s - - serial clock cycle time 1 t cyce 1 30t clk 32t clk 34t clk s l l serial clock cycle time 2 t cyce 2 62t clk 64t clk 66t clk s l h serial clock cycle time 3 t cyce 3 126t clk 128t clk 130t clk s h l serial clock cycle time 4 t cyce 4 254t clk 256t clk 258t clk s h h time length for data"1" 1 t hh 1 22t clk 24t clk 26t clk s l l time length for data ?1? 2 t hh 2 46t clk 48t clk 50t clk s l h time length for data ?1? 3 t hh 3 94t clk 96t clk 98t clk s h l time length for data ?1? 4 t hh 4 190t clk 192t clk 194t clk s h h time length for data ?0? 1 t lh 1 2t clk 4t clk 6t clk s l l time length for data ?0? 2 t lh 2 6t clk 8t clk 10t clk s l h time length for data ?0? 3 t lh 3 14t clk 16t clk 18t clk s h l time length for data ?0? 4 t lh 4 30t clk 32t clk 34t clk s h h rising time of serial clock tr - - 100 ns - - falling time of serial clock tf - - 100 ns - - *1: after ?display clear? instruction *2: after the instruction other than ?display clear?. t t clk = 1/fosc si data "1" si data "0" tr t cycen v il v ih tf v il v ih t hhn t lhn n=1~4 si 16bit 16bit t w - 38 - ver.2006-08-22 NJU6515 ? power supply startup (ta=-40 ~ +85 c) parameter symbol min typ max unit startup time of power supply tr dd 0.1 - 5 ms time for power supply off t off 1 - - ms if the above conditions cannot be met, the internal reset circuit will malfunction. vdd tr dd t off is the period when vdd is b elow than 0.2v during power temporarily blackout or power cycle on/off. 0.2v 1.5v t off -39- ver.2006-08-22 NJU6515 lcd driving voltage waveform (1) 1/9duty commk1 com1 com2 com3 com4 com5 com6 com7 commk2 seg 1 2 3 4 5 6 1 2 3 --- 7 mk1 mk2 123---7 mk1 mk2 1 vlcd v1 v2 v4 vss vlcd v1 v2 v4 vss vlcd v1 v2 v4 vss vlcd v1 v2 v4 vss vlcd v1 v2 v4 vss vlcd v1 v2 v4 vss vlcd v1 v2 v4 vss com7 commk1 commk2 seg1 seg2 com2 com1 - 40 - ver.2006-08-22 NJU6515 (2) 1/8duty commk1 com1 com2 com3 com4 com5 com6 com7 commk2 seg 1 2 3 4 5 6 1 2 3 --- 7 mk1 123---7 mk1 1 vlcd v1 v2 v4 vss vlcd v1 v2 v4 vss vlcd v1 v2 v4 vss vlcd v1 v2 v4 vss vlcd v1 v2 v4 vss vlcd v1 v2 v4 vss vlcd v1 v2 v4 vss com1 com2 com7 commk1 commk2 seg1 seg2 -41- ver.2006-08-22 NJU6515 application infromation (1-1) interface with lcd panel, sel1=0, sel2=0 (1-2) interface with lcd panel, sel1=1, sel2=1 commk1 com1 com7 commk2 seg1 seg6 seg59 NJU6515 top view seg1 seg6 seg59 NJU6515 top view commk1 com1 com7 commk2 - 42 - ver.2006-08-22 NJU6515 (1-3) interface with lcd panel, sel1=1, sel2=0 (1-4) interface with lcd panel, sel1=0, sel2=1 commk1 com1 com7 commk2 seg1 seg6 seg59 NJU6515 b o tt o m v ie w commk1 com1 com7 commk2 seg1 seg6 NJU6515 bottom view seg59 -43- ver.2006-08-22 NJU6515 (2-1) voltage boost on (x 3), regulator off, electrical volume on. (2-2) voltage boost on (x 2), regulator on, electrical volume on vdd vci vreg vout vlcd1 vss vlcd2 v1 v2 v4 vci=1.8v vdd=2v c1+ c1- c2+ c2- dc regon NJU6515 vdd vdd vci vreg vout vlcd1 vss vlcd2 v1 v2 v4 vci=3v vdd=3v c1+ c1- c2+ c2- dc regon NJU6515 vdd open - 44 - ver.2006-08-22 NJU6515 (2-3) voltage boost off, regulator off, electrical volume on (2-4) voltage boost off, regulator off, electrical volume off vdd vci vreg vout vlcd1 vss vlcd2 v1 v2 v4 vci=4v vdd=3v c1+ c1- c2+ c2- dc regon NJU6515 open vdd vci vreg vout vlcd1 vss vlcd2 v1 v2 v4 vci=4v vdd=3v c1+ c1- c2+ c2- dc regon NJU6515 open -45- ver.2006-08-22 NJU6515 (3-1) using external cr for oscillation (3-2) using external clock osc1 fsel NJU6515 vdd osc1 fsel NJU6515 clock vdd 51k 120pf - 46 - ver.2006-08-22 NJU6515 [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. |
Price & Availability of NJU6515
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |